1. Field of the Invention
This invention concerns the manufacture of a high-precision semiconductor printed circuit; in particular, it pertains to a manufacturing method for producing a deep-submicron P-type metal-oxide semiconductor (PMOS) transistor component.
2. Description of the Prior Art
In high-precision semiconductor printing circuits, especially for those produced by so-called deep-submicron technology, various issues generated during the downsizing of the component structure must be carefully examined. For example, due to the reduction in length of the passage area of the metal-oxide semiconductor, possible short channel effects must be considered. As a result, in order to complement the manufacture of smaller and more intricate semiconductors, various new technologies have been proposed.
The aforementioned short channel metal-oxide semiconductor components will be used as an example for further explanation. In short channel metal-oxide semiconductor components, problems pertaining to reliability that are most likely to occur include short channel effects. In particular, the thermoelectric effect may be improved by adjusting the structure of the diffusing area of the source pole and the supply pole, and much pertinent technology has been proposed for this purpose. To counteract the short channel effect, the primary method is to reduce the diffusing area's junction, i.e. using the shallow junction technology. However, with the continuous downsizing of component dimensions, in terms of the domain of deep-submicron technology, using traditional particle distribution planting methods to form a shallow junction is seemingly difficult. Especially, with respect to P-type metal-oxide semiconductor components, as the impurity diffusing area is formed by synthesizing with lighter-weight ions, such as boron ions, it is not easy to regulate the depth of diffusion within the tolerable range.
According to the above explanation, the manufacture of a PMOS component's shallow junction is indeed vital technology for controlling the component's reliability. Therefore, many pertinent technologies have been proposed to seek ways of improvement. For example, U.S. Pat. No. 5,443,994 describes a system that uses spacers, containing boron, as a diffusion source. FIG. 1 and FIG. 2 of the present application are sectional diagrams of the primary technique. A gate structure 12 is formed on the base plate or substrate 10, and boron synthesizing germanium (BSG) is used as the gate's side-wall spacer 14, as depicted in FIG. 1. This step is followed by distribution planting P-type conductive style impurity ions into the substrate 10, thereby forming a deep impurity diffusing source pole/drain pole P.sup.+ diffusing area 16. As shown in FIG. 2, a heating process is conducted to force the impurity contained in the side-wall spacer 14 to diffuse into the substrate 10, forming an extended diffusing area 18.
However, in the aforementioned manufacturing process, because the side wall spacer 14 is formed by a corrosion method, the thickness control is not sufficiently precise. This means it is not possible to control effectively the range of the extended diffusion area in the above-mentioned manufacturing method. As a result, the state of the impurity distribution in the transistor passage area will contain a large amount of variation, and this may harm the consistency of the component operating unit's characteristics. Furthermore, as the impurity diffuses directly into the substrate 10 via ion distributing planting, it may cause the depth of the P.sup.+ diffusing area 16 to be too deep, easily resulting in problems, such as punch-through, for the component, which also discredits its reliability.